## machcode-intel32.codemade.api
#
# This file generated at 2015-12-06:08:43:06 by
#
# src/lib/compiler/back/low/tools/arch/make-sourcecode-for-machcode-xxx-package.pkg#
# from the architecture description file
#
# src/lib/compiler/back/low/intel32/intel32.architecture-description
#
# Edits to this file will be LOST on next system rebuild.
# Compiled by:
# src/lib/compiler/back/low/intel32/backend-intel32.lib# This api specifies an abstract view of the INTEL32 instruction set.
#
# The idea is that the Base_Op sumtype defines
# one constructor for each INTEL32 machine instruction.
#
# Machcode allows us to do tasks like instruction selection and peephole optimization
# (not currently implemented) without yet worrying about the details of the actual
# target-architecture binary encoding of instructions.
#
# This file is a concrete instantiation of the general Machcode_Form api defined in:
#
# src/lib/compiler/back/low/code/machcode-form.api#
# At runtime our INTEL32 machcode representation of the program being compiled is produced by
#
# src/lib/compiler/back/low/intel32/treecode/translate-treecode-to-machcode-intel32-g.pkg#
# Later, absolute executable binary machine code is produced by
#
# src/lib/compiler/back/low/intel32/translate-machcode-to-execode-intel32-g.pkg#
# For display purposes, human-readable target-architecture assembly code is be produced
# from the machcode representation by
#
# src/lib/compiler/back/low/intel32/emit/translate-machcode-to-asmcode-intel32-g.codemade.pkg#
# This modules is mechanically generated from our architecture-description file by
#
# src/lib/compiler/back/low/tools/arch/make-sourcecode-for-translate-machcode-to-asmcode-xxx-g-package.pkg#
# This api is implemented in:
#
# src/lib/compiler/back/low/intel32/code/machcode-intel32-g.codemade.pkgstipulate
package lbl = codelabel; # codelabel is from src/lib/compiler/back/low/code/codelabel.pkg package nt = note; # note is from src/lib/src/note.pkg package rkj = registerkinds_junk; # registerkinds_junk is from src/lib/compiler/back/low/code/registerkinds-junk.pkgherein
api Machcode_Intel32 {
#
package rgk: Registerkinds_Intel32; # Registerkinds_Intel32 is from src/lib/compiler/back/low/intel32/code/registerkinds-intel32.codemade.pkg package tcf: Treecode_Form; # Treecode_Form is from src/lib/compiler/back/low/treecode/treecode-form.api package lac: Late_Constant; # Late_Constant is from src/lib/compiler/back/low/code/late-constant.api package rgn: Ramregion; # Ramregion is from src/lib/compiler/back/low/code/ramregion.api
sharing lac == tcf::lac; # "lac" == "late_constant".
sharing rgn == tcf::rgn; # "rgn" == "region".
Operand = IMMED one_word_int::Int
| IMMED_LABEL tcf::Label_Expression
| RELATIVE Int
| LABEL_EA tcf::Label_Expression
| DIRECT rkj::Codetemp_Info
| FDIRECT rkj::Codetemp_Info
| FPR rkj::Codetemp_Info
| ST rkj::Codetemp_Info
| RAMREG rkj::Codetemp_Info
| DISPLACE { base: rkj::Codetemp_Info,
disp: Operand,
ramregion: rgn::Ramregion
}
| INDEXED { base: Null_Or( (rkj::Codetemp_Info) ),
index: rkj::Codetemp_Info,
scale: Int,
disp: Operand,
ramregion: rgn::Ramregion
}
;
Addressing_Mode = Operand;
Effective_Address = Operand;
Cond = EQ
| NE
| LT
| LE
| GT
| GE
| BB
| BE
| AA
| AE
| CC
| NC
| PP
| NP
| OO
| NO
;
Binary_Op = ADDL
| SUBL
| ANDL
| ORL
| XORL
| SHLL
| SARL
| SHRL
| MULL
| IMULL
| ADCL
| SBBL
| ADDW
| SUBW
| ANDW
| ORW
| XORW
| SHLW
| SARW
| SHRW
| MULW
| IMULW
| ADDB
| SUBB
| ANDB
| ORB
| XORB
| SHLB
| SARB
| SHRB
| MULB
| IMULB
| BTSW
| BTCW
| BTRW
| BTSL
| BTCL
| BTRL
| ROLW
| RORW
| ROLL
| RORL
| XCHGB
| XCHGW
| XCHGL
| LOCK_ADCW
| LOCK_ADCL
| LOCK_ADDW
| LOCK_ADDL
| LOCK_ANDW
| LOCK_ANDL
| LOCK_BTSW
| LOCK_BTSL
| LOCK_BTRW
| LOCK_BTRL
| LOCK_BTCW
| LOCK_BTCL
| LOCK_ORW
| LOCK_ORL
| LOCK_SBBW
| LOCK_SBBL
| LOCK_SUBW
| LOCK_SUBL
| LOCK_XORW
| LOCK_XORL
| LOCK_XADDB
| LOCK_XADDW
| LOCK_XADDL
;
Mult_Div_Op = IMULL1
| MULL1
| IDIVL1
| DIVL1
;
Unary_Op = DECL
| INCL
| NEGL
| NOTL
| DECW
| INCW
| NEGW
| NOTW
| DECB
| INCB
| NEGB
| NOTB
| LOCK_DECL
| LOCK_INCL
| LOCK_NEGL
| LOCK_NOTL
;
Shift_Op = SHLDL
| SHRDL
;
Bit_Op = BTW
| BTL
| LOCK_BTW
| LOCK_BTL
;
Move = MOVL
| MOVB
| MOVW
| MOVSWL
| MOVZWL
| MOVSBL
| MOVZBL
;
Fbin_Op = FADDP
| FADDS
| FMULP
| FMULS
| FCOMS
| FCOMPS
| FSUBP
| FSUBS
| FSUBRP
| FSUBRS
| FDIVP
| FDIVS
| FDIVRP
| FDIVRS
| FADDL
| FMULL
| FCOML
| FCOMPL
| FSUBL
| FSUBRL
| FDIVL
| FDIVRL
;
Fibin_Op = FIADDS
| FIMULS
| FICOMS
| FICOMPS
| FISUBS
| FISUBRS
| FIDIVS
| FIDIVRS
| FIADDL
| FIMULL
| FICOML
| FICOMPL
| FISUBL
| FISUBRL
| FIDIVL
| FIDIVRL
;
Fun_Op = FCHS
| FABS
| FTST
| FXAM
| FPTAN
| FPATAN
| FXTRACT
| FPREM1
| FDECSTP
| FINCSTP
| FPREM
| FYL2XP1
| FSQRT
| FSINCOS
| FRNDINT
| FSCALE
| FSIN
| FCOS
;
Fenv_Op = FLDENV
| FNLDENV
| FSTENV
| FNSTENV
;
Fsize = FP32
| FP64
| FP80
;
Isize = INT8
| INT16
| INT1
| INT2
;
Base_Op = NOP
| JMP (Operand, List( lbl::Codelabel ))
| JCC { cond: Cond,
operand: Operand
}
| CALL { operand: Operand,
defs: rgk::Codetemplists,
uses: rgk::Codetemplists,
return: rgk::Codetemplists,
cuts_to: List( lbl::Codelabel ),
ramregion: rgn::Ramregion,
pops: one_word_int::Int
}
| ENTER { src1: Operand,
src2: Operand
}
| LEAVE
| RET Null_Or( Operand )
| MOVE { mv_op: Move,
src: Operand,
dst: Operand
}
| LEA { r32: rkj::Codetemp_Info,
address: Operand
}
| CMPL { lsrc: Operand,
rsrc: Operand
}
| CMPW { lsrc: Operand,
rsrc: Operand
}
| CMPB { lsrc: Operand,
rsrc: Operand
}
| TESTL { lsrc: Operand,
rsrc: Operand
}
| TESTW { lsrc: Operand,
rsrc: Operand
}
| TESTB { lsrc: Operand,
rsrc: Operand
}
| BITOP { bit_op: Bit_Op,
lsrc: Operand,
rsrc: Operand
}
| BINARY { bin_op: Binary_Op,
src: Operand,
dst: Operand
}
| SHIFT { shift_op: Shift_Op,
src: Operand,
dst: Operand,
count: Operand
}
| CMPXCHG { lock: Bool,
size: Isize,
src: Operand,
dst: Operand
}
| MULTDIV { mult_div_op: Mult_Div_Op,
src: Operand
}
| MUL3 { dst: rkj::Codetemp_Info,
src2: one_word_int::Int,
src1: Operand
}
| UNARY { un_op: Unary_Op,
operand: Operand
}
| SET { cond: Cond,
operand: Operand
}
| CMOV { cond: Cond,
src: Operand,
dst: rkj::Codetemp_Info
}
| PUSHL Operand
| PUSHW Operand
| PUSHB Operand
| PUSHFD
| POPFD
| POP Operand
| CDQ
| INTO
| FBINARY { bin_op: Fbin_Op,
src: Operand,
dst: Operand
}
| FIBINARY { bin_op: Fibin_Op,
src: Operand
}
| FUNARY Fun_Op
| FUCOM Operand
| FUCOMP Operand
| FUCOMPP
| FCOMPP
| FCOMI Operand
| FCOMIP Operand
| FUCOMI Operand
| FUCOMIP Operand
| FXCH { operand: rkj::Codetemp_Info }
| FSTPL Operand
| FSTPS Operand
| FSTPT Operand
| FSTL Operand
| FSTS Operand
| FLD1
| FLDL2E
| FLDL2T
| FLDLG2
| FLDLN2
| FLDPI
| FLDZ
| FLDL Operand
| FLDS Operand
| FLDT Operand
| FILD Operand
| FILDL Operand
| FILDLL Operand
| FNSTSW
| FENV { fenv_op: Fenv_Op,
operand: Operand
}
| FMOVE { fsize: Fsize,
src: Operand,
dst: Operand
}
| FILOAD { isize: Isize,
ea: Operand,
dst: Operand
}
| FBINOP { fsize: Fsize,
bin_op: Fbin_Op,
lsrc: Operand,
rsrc: Operand,
dst: Operand
}
| FIBINOP { isize: Isize,
bin_op: Fibin_Op,
lsrc: Operand,
rsrc: Operand,
dst: Operand
}
| FUNOP { fsize: Fsize,
un_op: Fun_Op,
src: Operand,
dst: Operand
}
| FCMP { i: Bool,
fsize: Fsize,
lsrc: Operand,
rsrc: Operand
}
| SAHF
| LAHF
| SOURCE { }
| SINK { }
| PHI { }
;
Machine_Op
= LIVE { regs: rgk::Codetemplists, spilled: rgk::Codetemplists }
| DEAD { regs: rgk::Codetemplists, spilled: rgk::Codetemplists }
#
| COPY { kind: rkj::Registerkind,
size_in_bits: Int,
dst: List( rkj::Codetemp_Info ),
src: List( rkj::Codetemp_Info ),
tmp: Null_Or( Effective_Address ) # NULL if |dst| == |src| == 1
}
#
| NOTE { op: Machine_Op,
note: nt::Note
}
#
| BASE_OP Base_Op
;
nop: Machine_Op;
jmp: (Operand, List( lbl::Codelabel )) -> Machine_Op;
jcc: { cond: Cond,
operand: Operand
}
-> Machine_Op;
call: { operand: Operand,
defs: rgk::Codetemplists,
uses: rgk::Codetemplists,
return: rgk::Codetemplists,
cuts_to: List( lbl::Codelabel ),
ramregion: rgn::Ramregion,
pops: one_word_int::Int
}
-> Machine_Op;
enter: { src1: Operand,
src2: Operand
}
-> Machine_Op;
leave: Machine_Op;
ret: Null_Or( Operand ) -> Machine_Op;
move: { mv_op: Move,
src: Operand,
dst: Operand
}
-> Machine_Op;
lea: { r32: rkj::Codetemp_Info,
address: Operand
}
-> Machine_Op;
cmpl: { lsrc: Operand,
rsrc: Operand
}
-> Machine_Op;
cmpw: { lsrc: Operand,
rsrc: Operand
}
-> Machine_Op;
cmpb: { lsrc: Operand,
rsrc: Operand
}
-> Machine_Op;
testl: { lsrc: Operand,
rsrc: Operand
}
-> Machine_Op;
testw: { lsrc: Operand,
rsrc: Operand
}
-> Machine_Op;
testb: { lsrc: Operand,
rsrc: Operand
}
-> Machine_Op;
bitop: { bit_op: Bit_Op,
lsrc: Operand,
rsrc: Operand
}
-> Machine_Op;
binary: { bin_op: Binary_Op,
src: Operand,
dst: Operand
}
-> Machine_Op;
shift: { shift_op: Shift_Op,
src: Operand,
dst: Operand,
count: Operand
}
-> Machine_Op;
cmpxchg: { lock: Bool,
size: Isize,
src: Operand,
dst: Operand
}
-> Machine_Op;
multdiv: { mult_div_op: Mult_Div_Op,
src: Operand
}
-> Machine_Op;
mul3: { dst: rkj::Codetemp_Info,
src2: one_word_int::Int,
src1: Operand
}
-> Machine_Op;
unary: { un_op: Unary_Op,
operand: Operand
}
-> Machine_Op;
set: { cond: Cond,
operand: Operand
}
-> Machine_Op;
cmov: { cond: Cond,
src: Operand,
dst: rkj::Codetemp_Info
}
-> Machine_Op;
pushl: Operand -> Machine_Op;
pushw: Operand -> Machine_Op;
pushb: Operand -> Machine_Op;
pushfd: Machine_Op;
popfd: Machine_Op;
pop: Operand -> Machine_Op;
cdq: Machine_Op;
into: Machine_Op;
fbinary: { bin_op: Fbin_Op,
src: Operand,
dst: Operand
}
-> Machine_Op;
fibinary: { bin_op: Fibin_Op,
src: Operand
}
-> Machine_Op;
funary: Fun_Op -> Machine_Op;
fucom: Operand -> Machine_Op;
fucomp: Operand -> Machine_Op;
fucompp: Machine_Op;
fcompp: Machine_Op;
fcomi: Operand -> Machine_Op;
fcomip: Operand -> Machine_Op;
fucomi: Operand -> Machine_Op;
fucomip: Operand -> Machine_Op;
fxch: { operand: rkj::Codetemp_Info } -> Machine_Op;
fstpl: Operand -> Machine_Op;
fstps: Operand -> Machine_Op;
fstpt: Operand -> Machine_Op;
fstl: Operand -> Machine_Op;
fsts: Operand -> Machine_Op;
fld1: Machine_Op;
fldl2e: Machine_Op;
fldl2t: Machine_Op;
fldlg2: Machine_Op;
fldln2: Machine_Op;
fldpi: Machine_Op;
fldz: Machine_Op;
fldl: Operand -> Machine_Op;
flds: Operand -> Machine_Op;
fldt: Operand -> Machine_Op;
fild: Operand -> Machine_Op;
fildl: Operand -> Machine_Op;
fildll: Operand -> Machine_Op;
fnstsw: Machine_Op;
fenv: { fenv_op: Fenv_Op,
operand: Operand
}
-> Machine_Op;
fmove: { fsize: Fsize,
src: Operand,
dst: Operand
}
-> Machine_Op;
fiload: { isize: Isize,
ea: Operand,
dst: Operand
}
-> Machine_Op;
fbinop: { fsize: Fsize,
bin_op: Fbin_Op,
lsrc: Operand,
rsrc: Operand,
dst: Operand
}
-> Machine_Op;
fibinop: { isize: Isize,
bin_op: Fibin_Op,
lsrc: Operand,
rsrc: Operand,
dst: Operand
}
-> Machine_Op;
funop: { fsize: Fsize,
un_op: Fun_Op,
src: Operand,
dst: Operand
}
-> Machine_Op;
fcmp: { i: Bool,
fsize: Fsize,
lsrc: Operand,
rsrc: Operand
}
-> Machine_Op;
sahf: Machine_Op;
lahf: Machine_Op;
source: { } -> Machine_Op;
sink: { } -> Machine_Op;
phi: { } -> Machine_Op;
};
end;